View PUCC23513DWY_9063122.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. ucc23513 slusd31 ? october 2018 ucc23513 3-a, 5-kv rms opto-compatible single channel isolated gate driver 1 1 features 1 ? 5-kv rms single channel isolated gate driver with an opto-compatible input ? 3-a maximum peak output current ? 13.2-v to 33-v output driver supply voltage ? 115-ns (maximum) propagation delay ? 25-ns (maximum) part-to-part delay matching ? 100-kv/ s minimum common-mode transient immunity (cmti) ? isolation barrier life > 40 years ? 7-v reverse polarity voltage handling capability on input pins ? stretched so-6 package with > 8.5-mm creepage and clearance ? operating junction temperature, t j : ? 40 c to +130 c ? safety-related certifications: ? v iso : 5-kv rms isolation voltage for 1 minute per ul 1577 ? v iosm : 8-kv pk isolation surge withstand voltage ? v iowm : 1-kv working voltage ? csa component acceptance notice 5 a, iec 60950-1 and iec 61010-1 end equipment standards (planned) ? cqc certification per gb4943.1-2011 (planned) 2 applications ? industrial motor-control drives ? industrial power supplies, ups ? solar inverters ? induction heating 3 description the ucc23513 is an opto compatible, single- channel, isolated igbt, sic, and mosfet gate driver with 3-a peak output current and 5kv rms reinforced isolation rating. the high supply voltage range of 33 v allows the use of bipolar supplies to effectively drive sic power fets. ucc23513 can drive both high side (with external boot strap diode and capacitor) and low side power fets. key features and characteristics bring significant performance and reliability upgrades over standard opto-coupler based gate drivers while maintaining pin-to-pin compatibility in both schematic and layout design. performance highlights include high common mode transient immunity (cmti), low propagation delay, and small pulse width distortion. tight process control means small part-to-part skew. the input stage is an emulated diode (ediode) which means long term reliability and excellent aging characteristics over traditional leds. in addition, the material group i mold compound and resulting comparative tracking index (cti) of > 600 v means robust insulating material. ucc23513 ? s high performance and reliability along with its stretched so-6 package, > 8.5-mm clearance and creepage makes it suitable for inverter applications in motor drive and solar, dc motor control, industrial power supplies, and appliances. the higher operating temperature opens up opportunities for applications not previously able to be supported by traditional optocouplers. device information (1) part number package body size (nom) ucc23513 stretched so-6 7.5 mm x 4.68 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. functional block diagram of ucc23513 (so6) 1 2 3 6 5 4 e anode nc cathode v cc v out v ee uvlo isolation barrier advance information tools & software technical documents ordernow productfolder support &community
2 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and function ........................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 power ratings ........................................................... 4 6.6 electrical characteristics ........................................... 7 6.7 switching characteristics .......................................... 7 6.8 typical characteristics .............................................. 8 7 parameter measurement information .................. 9 7.1 propagation delay, rise time and fall time ................ 9 7.2 i oh and i ol testing ..................................................... 9 7.3 cmti testing ............................................................. 9 8 detailed description ............................................ 10 8.1 overview ................................................................. 10 8.2 functional block diagram ....................................... 10 8.3 feature description ................................................. 11 8.4 device functional modes ........................................ 15 9 application and implementation ........................ 16 9.1 application information ............................................ 16 9.2 typical application ................................................. 17 10 power supply recommendations ..................... 22 11 layout ................................................................... 23 11.1 layout guidelines ................................................. 23 11.2 layout example .................................................... 24 11.3 pcb material ......................................................... 27 12 mechanical, packaging, and orderable information ........................................................... 27 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes october 2018 * advance information release. advance information
3 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and function ucc23513 package so-6 top view (1) p = power, g = ground, i = input, o = output pin functions pin type (1) description name no. ucc23513 anode 1 i anode nc 2 - no connection cathode 3 i cathode v ee 4 p negative output supply rail v out 5 o gate-drive output v cc 6 p positive output supply rail advance information 1 2 3 6 5 4 anode nc cathode v cc v out v ee
4 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) to maintain the recommended operating conditions for t j , see the thermal information . 6 specifications 6.1 absolute maximum ratings over operating free air temperature range (unless otherwise noted) (1) min max unit average input current i f(avg) - 25 ma peak transient input current i f(tran) < 1us pulse, 300pps 1 a reverse input voltage v r(max) - 7 v output supply voltage v cc ? v ee ? 0.3 35 v output signal voltage v out ? v cc 0.3 v output signal voltage v out ? v ee -0.3 v junction temperature t j (2) ? 55 130 c storage temperature t stg -55 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js ? 001 (1) 2000 v charged device model (cdm), per jedec specification jesd22- c101 (2) 1000 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v cc output supply voltage (v cc ? v ee ) 13.2 33 v i f (on) input diode forward current (diode "on") 7 16 ma i f (off) anode voltage -cathode voltage (diode "off") -5 0.8 v t j junction temperature ? 40 130 c t a ambient temperature ? 40 115 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) so-6 unit r ja junction ? to-ambient thermal resistance 126 c/w r jc(top) junction ? to-case (top) thermal resistance 66.1 c/w r jb junction ? to-board thermal resistance 62.8 c/w jt junction ? to-top characterization parameter 29.6 c/w jb junction ? to-board characterization parameter 60.8 c/w 6.5 power ratings parameter test conditions min typ max unit p d maximum power dissipation on input and output v cc = 15 v, i f = 10ma 42-khz, 50% duty cycle, square wave,100-nf load 833 mw p d1 maximum input power dissipation 10 mw p d2 maximum output power dissipation 823 mw advance information
5 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. (2) testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (3) apparent charge is electrical discharge caused by a partial discharge (pd). (4) all pins on each side of the barrier tied together creating a two-pin device. table 1. insulation specifications parameter test conditions value unit clr external clearance (1) shortest terminal-to-terminal distance through air > 8.5 mm cpg external creepage (1) shortest terminal-to-terminal distance across the package surface > 8.5 mm dti distance through the insulation minimum internal gap (internal clearance) > 21 m cti comparative tracking index din en 60112 (vde 0303-11); iec 60112 > 600 v material group i overvoltage category rated mains voltage 600v rms i-iv rated mains voltage 1000 v rms i-iii din v vde 0884-10 (vde v 0884-10) v iorm maximum repetitive peak isolation voltage ac voltage (bipolar) 1414 v pk v iowm maximum isolation working voltage ac voltage (sine wave); time-dependent dielectric breakdown (tddb) test 1000 v rms dc voltage 1414 v dc v iotm maximum transient isolation voltage v test = v iotm 7071 v pk v iosm maximum surge isolation voltage (2) test method per iec 60065, 1.2/50 s waveform, v test = 1.6 v iosm = 12.8 kv pk (qualification) 8000 v pk q pd apparent charge (3) method a: after i/o safety test subgroup 2/3,v ini = v iotm , t ini = 60 s; v pd(m) = 1.2 v iorm = 1696 v pk , t m = 10 s 5 pc method a: after environmental tests subgroup 1, v ini = v iotm , t ini = 60 s; v pd(m) = 1.6 v iorm = 2262 v pk , t m = 10 s 5 method b1: at routine test (100% production) and preconditioning (type test), v ini = v iotm , t ini = 1 s; v pd(m) = 1.875 v iorm = 2651 v pk , t m = 1 s 5 c io barrier capacitance, input to output (4) v io = 0.4 sin (2 ft), f = 1 mhz 1.0 pf r io insulation resistance, input to output (4) v io = 500 v, t a = 25 c > 10 12 v io = 500 v, 100 c t a 125 c > 10 11 v io = 500 v at t s = 150 c > 10 9 pollution degree 2 climatic category 55/125/21 ul 1577 v iso withstand isolation voltage v test = v iso = 5000 v rms , t = 60 s (qualification); v test = 1.2 v iso = 6000 v rms , t = 1 s (100% production) 5000 v rms table 2. safety-related certifications vde csa ul cqc tuv plan to certify according to din v vde v 0884-10 (vde v 0884-10):2006- 12 and din en 61010-1 (vde 0411-1):2011-07 plan to certify under csa component acceptance notice 5a, iec 60950-1, and iec 61010-1 plan to certify according to ul 1577 component recognition program plan to certify according to gb4943.1-2011 plan to certify according to en 61010-1:2010 (3rd ed) and en 60950- 1:2006/a11:2009/a1:2010 /a12:2011/a2:2013 certificate planned certificate planned certificate planned certificate planned certificate planned advance information
6 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated table 3. safety limiting values parameter test conditions min typ max unit first section i s safety input, output, or supply current r ja = 126 c/w, v i = 15 v, t j = 130 c, t a = 25 c 55 ma r ja = 126 c/w, v i = 30 v, t j = 130 c, t a = 25 c 28 p s safety input, output, or total power r ja = 126 c/w, t j = 130 c, t a = 25 c 833 mw t s maximum safety temperature 130 c advance information
7 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.6 electrical characteristics unless otherwise noted, all typical values are at t a = 25 c, v cc ? v ee = 15v, v ee = gnd. all min and max specifications are at recommended operating conditions (t j = -40c to 130 c, i f(on) = 7 ma to 16 ma, v ee = gnd, v cc = 15 v to 30 v, v f(off) = ? 5v to 0.8v) parameter test conditions min typ max unit input i flh input forward threshold current low to high v out > 5 v, cg = 1 nf 2.2 4 ma v f input forward voltage 7 ma i f 16 ma 1.8 2.0 2.2 v v f_hl threshold input voltage high to low v > 5 v, cg = 1 nf 0.8 v v f / t temp coefficient of input forward voltage 7 ma i f 16 ma -1 0 1 mv/ o c v r input reverse breakdown voltage i r = 10 ua 8 v c in input capacitance f = 1 mhz, v f = 0 v 15 pf output i oh high level peak output current i f = 7 ma, v cc =15v, c load =0.18uf, c vdd =10uf 4.5 a i ol low level peak output current v f = 0 v, v cc =15v, c load =0.18uf, c vdd =10uf 5.3 a v oh high level output voltage i f = 10 ma, i o = -20ma (with respect to vcc) 0.07 0.18 0.36 v i f = 10 ma, i o = 0 ma vcc v v ol low level output voltage v f = 0 v, i o = 20 ma 25 mv i cc_h output supply current (diode on) i f = 10 ma, i o = 0 ma 2.2 ma i cc_l output supply current (diode off) v f = 0 v, i o = 0 ma 2 ma under voltage lockout uvlo r under voltage lockout vcc rising v cc_rising, i f =10 ma 10.5 11.75 13 v uvlo f under voltage lockout vcc falling v cc_falling , i f =10 ma 9.5 10.75 12 v uvlo hys uvlo hysteresis 1.0 v (1) t sk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads ensured by characterization. 6.7 switching characteristics unless otherwise noted, all typical values are at t a = 25 c, v cc -v ee = 30 v, v ee = gnd. all min and max specifications are at recommended operating conditions (t j = -40 to 130 c, i f(on) = 7 ma to 16 ma, v ee = gnd, v cc = 15 v to 30 v, v f(off) = ? 5v to 0.8v) parameter test conditions min typ max unit t r output-signal rise time cg = 1nf f sw = 20 khz, (50% duty cycle) vcc=15v 28 ns t f output-signal fall time 25 ns t plh propagation delay, high 70 115 ns t phl propagation delay, low 70 115 ns t pwd pulse width distortion |t phl ? t plh | 35 ns t sk(pp) part-to-part skew in propagation delay between any two parts (1) 1 25 ns t uvlo_rec uvlo recovery delay of v cc (rising from 0v to 15v) 25 s cmti h common-mode transient immunity (output high) i f = 10 ma, v cm = 1500 v, v cc = 30 v, t a = 25 o c 100 kv/ s cmti l common-mode transient immunity (output low) v f = 0 v, v cm = 1500 v, v cc = 30 v, t a = 25 o c 100 kv/ s advance information
8 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.8 typical characteristics v cc = 15 v, 1- f capacitor from v cc to v ee , c load = 1 nf for timing tests and 180nf for i oh and i ol tests, t a = ? 40 c to +130 c, (unless otherwise noted) c load = 180-nf figure 1. output drive currents (i oh and i ol ) versus temperature figure 2. supply currents (i cch and i ccl ) versus temperature figure 3. supply current (i cch and i ccl )versus supply voltage figure 4. forward threshold current (i flh ) versus temperature c load = 1-nf figure 5. propagation delay (t pdlh , t pdhl ) versus temperature c load = 1-nf figure 6. propagation delay versus forward current (i f ) temp q current (ma) -40 -20 0 20 40 60 80 100 120 140 160 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 d002 i cc h i cc l temp q c current (ma) -40 -20 0 20 40 60 80 100 120 140 160 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15 d004 temp q c peak current (a) -40 -20 0 20 40 60 80 100 120 140 160 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 d001 ioh iol i f (ma) delay (ns) 6 8 10 12 14 16 18 20 22 24 26 58 60 62 64 66 68 70 72 74 76 d006d006 tpdlh tpdhl v cc current (ma) 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 1.075 1.1 1.125 1.15 1.175 1.2 1.225 1.25 1.275 1.3 1.325 d003 i cc h i cc l advance information temp q c delay (ns) -40 -20 0 20 40 60 80 100 120 140 160 60 62 64 66 68 70 72 74 76 78 80 d005d005 t pdlh t pdhl
9 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 parameter measurement information 7.1 propagation delay, rise time and fall time figure 7 shows the propagation delay from the input forward current i f , to v out . this figures also shows the circuit used to measure the rise (t r ) and fall (t f ) times and the propagation delays t pdlh and t pdhl . figure 7. i f to v out propagation delay, rise time and fall time 7.2 i oh and i ol testing figure 8 shows the circuit used to measure the output drive currents i oh and i ol . a load capacitance of 180nf is used at the output. the peak dv/dt of the capacitor voltage is measured in order to determine the peak source and sink currents of the gate driver. figure 8. i oh and i ol 7.3 cmti testing figure 9 is the simplified diagram of the cmti testing. common mode voltage is set to 1500v. the test is performed with i f = 6ma (vout= high) and i f = 0ma (v out = low). the diagram also shows the fail criteria for both cases. during the application on the cmti pulse with i f = 6ma, if v out drops from vcc to ? vcc it is considered as a failure. with i f = 0ma, if v out rises above 1v, it is considered as a failure. figure 9. cmti test circuit for ucc23513 1 2 3 6 5 4 e anode nc v cc v ee isolation barrier cathode 150 q i f v out + - 15v 1nf 150 q + - 5v v cm =1500v 1500v 0v 30v 0v v out fail threshold 15v v cm t 1500v 0v 0v v out fail threshold 1v t v cm e-diode on e-diode off advance information 1 2 3 6 5 4 e anode nc v cc v ee isolation barrier cathode 270 q i f v out + - 5 0 15v 1nf t pd_lh i f v out t pd_hl t r t f 80% 50% 20% 1 2 3 6 5 4 e anode nc v cc v ee isolation barrier cathode 270 q i f v out 5 0 180nf i oh i ol + - 15v
10 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview ucc23513 is a single channel isolated gate driver, with an opto compatible input stage, that can drive igbts, mosfets and sic fets. it has 3a of peak output current capability with max output driver supply voltage of 33v. the inputs and the outputs are galvanically isolated. ucc23513 is offered in an industry standard 6 pin (so6) package with > 8.5mm creepage and clearance. it has a working voltage of 1000v rms , reinforced isolation rating of 5kv rms for 60s and a surge rating of 8kv pk . it is pin to pin compatible with standard opto isolated gate drivers. while standard opto isolated gate drivers use an led as the input stage, ucc23513 uses an emulated diode (or "e-diode") as the input stage which does not use light emission to transmit signals across the isolation barrier. the input stage is isolated from the driver stage by dual, series hv sio 2 capacitors in full differential configuration that not only provides reinforced isolation but also offers best in class common mode transient immunity of > 100kv/us. the e-diode input stage along with capacitive isolation technology, gives ucc23513 several performance advantages over standard opto isolated gate drivers. they are as follows: 1. since the e-diode does not use light emission for its operation, the reliability and aging characteristics of ucc23513 are naturally superior to those of standard opto isolated gate drivers. 2. higher ambient operating temperature range of 115 c, compared to only 105 c for opto isolated gate drivers 3. the e-diode forward voltage drop has less part to part variation and smaller variation across temperature. hence the operating point of the input stage is more stable and predictable across different parts and operating temperature. 4. higher common mode transient immunity than opto isolated gate drivers 5. smaller propagation delay than opto isolated gate drivers 6. due to superior process controls achievable in capacitive isolation compared to opto isolation, there is less part to part skew in the prop delay, making the system design simpler and more robust 7. smaller pulse width distortion than opto isolated gate drivers the signal across the isolation has an on-off keying (ook) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier (see figure 10 ). the transmitter sends a high-frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. the receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. the ucc23513 also incorporates advanced circuit techniques to maximize the cmti performance and minimize the radiated emissions from the high frequency carrier and io buffer switching. figure 11 shows conceptual detail of how the ook scheme works. 8.2 functional block diagram figure 10. conceptual block diagram of a isolated gate driver with an opto emulated input stage (so6 pkg) advance information v clamp bias generation lc oscillator demodulator amplifier v bias i f v cc v ee transmitter receiver anode cathode uvlo v ee isolation barrier v out nc level shift / pre driver r nmos r oh r ol
11 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated functional block diagram (continued) figure 11. on-off keying (ook) based modulation scheme 8.3 feature description 8.3.1 power supply since the input stage is an emulated diode, no power supply is needed at the input. the output supply, v cc , supports a voltage range from 13.2 v to 33 v. for operation with bipolar supplies, the power device is turned off with a negative voltage on the gate with respect to the emitter or source. this configuration prevents the power device from unintentionally turning on because of current induced from the miller effect. the typical values of the v cc and v ee output supplies for bipolar operation are 15 v and ? 8 v with respect to gnd for igbts, and 20 v and ? 5 v for sic mosfets. for operation with unipolar supply, the v cc supply is connected to 15 v with respect to gnd for igbts, and 20 v for sic mosfets. the v ee supply is connected to 0v. 8.3.2 input stage the input stage of ucc23513 is simply the e-diode and therefore has an anode (pin 1) and a cathode (pin 3). pin 2 has no internal connection and can be left open or connected to ground. the input stage does not have a power and ground pin. when the e-diode is forward biased by applying a positive voltage to the anode with respect to the cathode, a forward current i f flows into the e-diode. the forward voltage drop across the e-diode is typically 2.0v. an external resistor should be used to limit the forward current. the recommended range for the forward current is 7ma to 16ma. when i f exceeds the threshold current i flh (2.5ma typ.) a high frequency signal is transmitted across the isolation barrier through the hv sio 2 capacitors. the hf signal is detected by the receiver and v out is driven high. see selecting the input resistor for information on selecting the input resistor. the dynamic impedance of the e-diode is very small( < 1.0 ? ) and the temperature coefficient of the e-diode forward voltage drop is < 1mv/ c. this leads to excellent stability of the forward current i f across all operating conditions. if the anode voltage drops below v f_hl (0.8v typ.), or reverse biased, the gate driver output is driven low. the reverse breakdown voltage of the e-diode is > 8v. so for normal operation, a reverse bias of 5v is permissible. the large reverse breakdown voltage of the e-diode also enables ucc23513 to be operated in interlock architecture (see example in figure 12 ). this example shows two gate drivers driving a set of igbts. the inputs of the gate drivers are connected as shown and driven by two buffers that are controlled by the mcu. interlock architecture prevents both the e-diodes from being "on" at the same time, preventing shoot through in the igbts. it also ensures that if both pwm signals are erroneously stuck high (or low) simultaneously, both gate driver outputs will be driven low. advance information i f in carrier signal through isolation barrier rx out
12 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) figure 12. interlock 8.3.3 output stage the output stages of the ucc23513 family feature a pullup structure that delivers the highest peak-source current when it is most needed which is during the miller plateau region of the power-switch turnon transition (when the power-switch drain or collector voltage experiences dv/dt). the output stage pullup structure features a p-channel mosfet and an additional pullup n-channel mosfet in parallel. the function of the n-channel mosfet is to provide a brief boost in the peak-sourcing current, enabling fast turnon. fast turnon is accomplished by briefly turning on the n-channel mosfet during a narrow instant when the output is changing states from low to high. the on-resistance of this n-channel mosfet (r nmos ) is approximately 5.1 when activated. table 4. ucc23513 on-resistance r nmos r oh r ol unit 5.1 9.5 0.40 the r oh parameter is a dc measurement and is representative of the on-resistance of the p-channel device only. this parameter is only for the p-channel device because the pullup n-channel device is held in the off state in dc condition and is turned on only for a brief instant when the output is changing states from low to high. therefore, the effective resistance of the ucc23513 pullup stage during this brief turnon phase is much lower than what is represented by the r oh parameter, yielding a faster turn on. the turnon-phase output resistance is the parallel combination r oh || r nmos . 1 2 3 6 5 4 e anode nc cathode v cc v out v ee isolation barrier r1 1 2 3 6 5 4 e anode nc cathode v cc v out v ee uvlo isolation barrier r2 to high side gate to low side gate v sup hson from mcu gnd v sup lson from mcu gnd uvlo advance information
13 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated the pulldown structure in the ucc23513 is simply composed of an n-channel mosfet. the output voltage swing between v cc and v ee provides rail-to-rail operation because of the mos-out stage which delivers very low dropout. figure 13. output stage 8.3.4 protection features 8.3.4.1 undervoltage lockout (uvlo) uvlo function is implemented for v cc and v ee pins to prevent an underdriven condition on igbts and mosfets. when v cc is lower than uvlo r at device start-up or lower than uvlo f after start-up, the voltage- supply uvlo feature holds the effected output low, regardless of the input forward current as shown in table 5 . the v cc1 uvlo protection has a hysteresis feature (uvlo hys ). this hysteresis prevents chatter when the power supply produces ground noise which allows the device to permit small drops in bias voltage, which occurs when the device starts switching and operating current consumption increases suddenly. when v cc drops below uvlo f , a delay, t uvlo_rec occurs on the output when the supply voltage rises above uvlo r again. advance information demodulator v cc v ee uvlo v ee level shift / pre driver r nmos r oh r ol v out
14 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 14. uvlo functionality 8.3.4.2 active pulldown the active pulldown function is used to pull the igbt or mosfet gate to the low state when no power is connected to the v cc supply. this feature prevents false igbt and mosfet turnon by clamping v out pin to approximately 2 v. when the output stages of the driver are in an unbiased or uvlo condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs. in this condition, the upper pmos is resistively held off by a pullup resistor while the lower nmos gate is tied to the driver output through a 500-k resistor. in this configuration, the output is effectively clamped to the threshold voltage of the lower nmos device which is typically less than 1.5 v when no bias power is available. 8.3.4.3 short-circuit clamping the short-circuit clamping function is used to clamp voltages at the driver output and pull the output pin v out slightly higher than the v cc voltage during short-circuit conditions. the short-circuit clamping function helps protect the igbt or mosfet gate from overvoltage breakdown or degradation. the short-circuit clamping function is implemented by adding a diode connection between the dedicated pins and the v cc pin inside the driver. the internal diodes can conduct up to 500-ma current for a duration of 10 s and a continuous current of 20 ma. use external schottky diodes to improve current conduction capability as needed. v cc t uvlo f v out t uvlo_rec uvlo r advance information
15 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.4 device functional modes table 5 lists the functional modes for ucc23513 table 5. function table for ucc23513 with vcc rising e-diode vcc v out off (i f < i flh ) 0v - 33v low on (i f > i flh ) 0v - uvlo r low on ( (i f > i flh ) uvlo r - 33v high table 6. function table for ucc23513 with vcc falling e-diode vcc v out off (i f < i flh ) 0v - 33v low on (i f > i flh ) uvlo f - 0v low on ( (i f > i flh ) 33v - uvlo f high 8.4.1 esd structure figure 15 shows the multiple diodes involved in the esd protection components of the ucc23513 device . this provides pictorial representation of the absolute maximum rating for the device. figure 15. esd structure advance information
16 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information ucc23513 is a single channel, isolated gate driver with opto compatible input for power semiconductor devices, such as mosfets, igbts, or sic mosfets. it is intended for use in applications such as motor control, industrial inverters, and switched-mode power supplies. it differs from standard opto isolated gate drivers as it does not have an led input stage. instead of an led, it has an emulated diode (e-diode). to turn the e-diode "on", a forward current in the range of 7ma to 16ma should be driven into the anode. this will drive the gate driver output high and turn on the power fet. typically, mcu's are not capable of providing the required forward current. hence a buffer has to be used between the mcu and the input stage of ucc23513. typical buffer power supplies are either 5v or 3.3v. a resistor is needed between the buffer and the input stage of ucc23513 to limit the current. it is simple, but important to choose the right value of resistance. the resistor tolerance, buffer supply voltage tolerance and output impedance of the buffer, have to be considered in the resistor selection. this will ensure that the e-diode forward current stays within the recommended range of 7ma to 16ma. detailed design recommendations are given in the application information . the current driven input stage offers excellent noise immunity that is need in high power motor drive systems, especially in cases where the mcu cannot be located close to the isolated gate driver. ucc23513 offers best in class cmti performance of > 100kv/us at 1500v common mode voltages. the e-diode is capable of 25ma continuous in the forward direction. the forward voltage drop of the e-diode has a very tight part to part variation (1.8v min to 2.2v max). the temperature coefficient of the forward drop is < 1mv/ c. the dynamic impedance of the e-diode in the forward biased region is < 1 . all of these factors contribute in excellent stability of the e-diode forward current across all operating conditions. to turn the e-diode "off", the anode - cathode voltage should be < 0.8v, or i f should be < i flh . the e-diode can also be reverse biased up to 5v (7v abs max) in order to turn it off and bring the gate driver output low. the output power supply for ucc23513 can be as high as 33v (35v abs max). the output power supply can be configured externally as a single isolated supply up to 33v or isolated bipolar supply such that vcc-vee does not exceed 33v, or it can be bootstrapped (with external diode & capacitor) if the system uses a single power supply with respect to the power ground. typical quiescent power supply current on vcc is 1ma (max 2.2ma). advance information
17 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2 typical application the circuit in figure 16 , shows a typical application for driving igbts. figure 16. typical application circuit for ucc23513 to drive igbt 9.2.1 design requirements table 7 lists the recommended conditions to observe the input and output of the ucc23513 gate driver. table 7. ucc23513 design requirements parameter value unit v cc 15 v i f 11 ma switching frequency 8 khz advance information + - 15v r gon 1 2 3 6 5 4 e anode nc v cc v ee isolation barrier cathode gnd r ext /2 pwm m1 i f v f + - r ext /2 v sup v out r goff
18 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.2 detailed design procedure 9.2.2.1 selecting the input resistor the input resistor limits the current that flows into the e-diode when it is forward biased. the threshold current i flh is 2.5ma typ. the recommended operating range for the forward current is 7ma to 16ma (e-diode on). all the electrical specifications are guaranteed in this range. the resistor should be selected such that for typical operating conditions, i f is 11ma. following are the list of factors that will affect the exact value of this current: 1. supply voltage v sup variation 2. manufacturer's tolerance for the resistor and variation due to temperature 3. e-diode forward voltage drop variation (2.0v typ, min 1.8v, max 2.2v, < 1mv/ c temperature coefficient and < 1 dynamic impedance) see figure 17 for the schematic using a single nmos and split resistor combination to drive the input stage of ucc23513. the input resistor can be selected using the equation shown. figure 17. driving the input stage of ucc23513 with a single nmos and split resistors driving the input stage of ucc23513 using a single buffer is shown in figure 18 and using 2 buffers is shown in figure 19 figure 18. driving the input stage of ucc23513 with one buffer and split resistors advance information 1 2 3 6 5 4 e anode nc v cc v ee isolation barrier cathode v sup i f v f + - gnd gnd r ext /2 r ext /2 pwm (from mcu) r ext = v sup f v f i f f r oh_buf 1 2 3 6 5 4 e anode nc v cc v ee isolation barrier cathode gnd r ext /2 pwm m1 i f v f + - r ext /2 v sup v out r ext = v sup f v f i f f r m1
19 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 19. driving the input stage of ucc23513 with 2 buffers and split resistors table 8 shows the range of values for r ext for the 3 different configurations shown in figure 17 , figure 18 and figure 19 .the assumptions used in deriving the range for r ext are as follows: 1. target forward current i f is 7ma min, 11ma typ and 16ma max 2. e-diode forward voltage drop is 1.8v to 2.2v 3. v sup (buffer supply voltage) is 5v with 5% tolerance 4. manufacturer's tolerance for r ext is 3% 5. nmos resistance is 0.25 to 1.0 (for configuration 1) 6. r oh (buffer output impedance in output "high" state) is 13 min, 18 typ and 22 max 7. r ol (buffer output impedance in "low" state) is 10 min, 14 typ and 17 max table 8. r ext values to drive the input stage r ext configuration min typ max single nmos and r ext 222 266 352 single buffer and r ext 208 249 332 two buffers and r ext 198 235 315 9.2.2.2 gate-driver output resistor the external gate-driver resistors, r g(on) and r g(off) are used to: 1. limit ringing caused by parasitic inductances and capacitances 2. limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery 3. fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss 4. reduce electromagnetic interference (emi) the output stage has a pull up structure consisting of a p-channel mosfet and an n-channel mosfet in parallel. the combined peak source current is 4.6 a use equation 1 to estimate the peak source current as an example. (1) where i oh = min h 4.5a, v cc (r nmos ||r oh + r gon + r gfet int ) i 1 2 3 6 5 4 e anode nc v cc v ee isolation barrier cathode v sup pwm (from mcu) i f v f + - gnd v sup pwm (from mcu) r ext /2 r ext /2 r ext = v sup f v f i f f (r oh_buf + r ol_buf ) advance information
20 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated ? r gon is the external turnon resistance. ? r gfet_int is the power transistor internal gate resistance, found in the power transistor data sheet. we will assume 0 for our example ? i oh is the peak source current which is the minimum value between 4.6a, the gate-driver peak source current, and the calculated value based on the gate-drive loop resistance. (2) in this example, the peak source current is approximately 1.8a as calculated in equation 3 . (3) similarly, use equation 4 to calculate the peak sink current. where ? r goff is the external turnoff resistance. ? i ol is the peak sink current which is the minimum value between 5.7a, the gate-driver peak sink current, and the calculated value based on the gate-drive loop resistance. (4) in this example, the peak sink current is the minimum of equation 5 and 5.7a. (5) note the estimated peak current is also influenced by pcb layout and load capacitance. parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. therefore, ti strongly recommends that the gate- driver loop should be minimized. conversely, the peak source and sink current is dominated by loop parasitics when the load capacitance (c iss ) of the power transistor is very small (typically less than 1 nf) because the rising and falling time is too small and close to the parasitic ringing period. 9.2.2.3 estimate gate-driver power loss the total loss, p g , in the gate-driver subsystem includes the power losses (p gd ) of the ucc23513 device and the power losses in the peripheral circuitry, such as the external gate-drive resistor. the p gd value is the key power loss which determines the thermal safety-related limits of the ucc23513 device, and it can be estimated by calculating losses from several components. the first component is the static power loss, p gdq , which includes power dissipated in the input stage (p gdq_in ) as well as the quiescent power dissipated in the output stage (p gdq_out ) when operating with a certain switching frequency under no load. p gdq_in is determined by i f and v f and is given by equation 6 . the p gdq_out parameter is measured on the bench with no load connected to v out pin at a given v cc , switching frequency, and ambient temperature. in this example, v cc is 15 v. the current on the power supply, with pwm switching at 10 khz, is measured to be i cc = 1.33 ma . therefore, use equation 7 to calculate p gdq_out . (6) (7) the total quiescent power (without any load capacitance) dissipated in the gate driver is given by the sum of equation 6 and equation 7 as shown in equation 8 p gdq _out = v cc * i cc p gdq _in = 1 2 ? v f * i f i ol = min h 5.3a, 15 (0. v + sr + r ) i = 1.44a i ol = min h 5.3a, v cc (r ol + r goff + r gfet int ) i advance information i oh = min h 4.5a, 15 (5. s ||9. w + w + r ) i = 1.8a
21 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated (8) the second component is the switching operation loss, p gdsw , with a given load capacitance which the driver charges and discharges the load during each switching cycle. use equation 9 to calculate the total dynamic loss from load switching, p gsw . where ? q g is the gate charge of the power transistor at v cc . (9) so, for this example application the total dynamic loss from load switching is approximately 18 mw as calculated in equation 10 . (10) q g represents the total gate charge of the power transistor switching 520 v at 50 a, and is subject to change with different testing conditions. the ucc23513 gate-driver loss on the output stage, p gdo , is part of p gsw . p gdo is equal to p gsw if the external gate-driver resistance and power-transistor internal resistance are 0 , and all the gate driver-loss will be dissipated inside the ucc23513. if an external turn-on and turn-off resistance exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power- transistor internal resistance. importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4.6a/5.7a, however, it will be non-linear if the source/sink current is saturated. therefore, p gdo is different in these two scenarios. case 1 - linear pull-up/down resistor: (11) in this design example, all the predicted source and sink currents are less than 4.6 a and 5.7 a, therefore, use equation 11 to estimate the ucc23513 gate-driver loss. (12) case 2 - nonlinear pull-up/down resistor: where ? v out(t) is the gate-driver out pin voltage during the turnon and turnoff period. in cases where the output is saturated for some time, this value can be simplified as a constant-current source (4.6 a at turnon and 5.7 a at turnoff) charging or discharging a load capacitor. then, the v out(t) waveform will be linear and the t r_sys and t f_sys can be easily predicted. (13) for some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the p gdo is a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based on this discussion. use equation 14 to calculate the total gate-driver loss dissipated in the ucc23513 gate driver, p gd . (14) 9.2.2.4 estimating junction temperature use equation 15 to estimate the junction temperature (t j ) of ucc23513. gsw p 15 v 120 nc 10 khz 18 mw u u cc2 gsw g sw p v q f u u p gdo = p gsw 2 h r oh ||r nmos r oh ||r nmos + r gon + r gfet_int + r ol r ol + r goff + r gfet_int i p gdq = p gdq _in + p gdq _out = 10 mw + 20mw = 30mw advance information p gdo = 18 mw 2 h 9.5 ||5.1 9.5 ||5.1 + 5.1 + 0 + 0.4 0.4 + 10 + 0 i = 3.9 mw p gdo = f sw x f 4.5a x (v cc t r _sys 0 f v out (t))dt + 5.3a x v out (t) t f_sys 0 dt j p gd = p gdq + p gdo = 30mw + 3.9mw = 33.9mw
22 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated where ? t c is the ucc23513 case-top temperature measured with a thermocouple or some other instrument. ? jt is the junction-to-top characterization parameter from the thermal information table. (15) using the junction-to-top characterization parameter ( jt ) instead of the junction-to-case thermal resistance (r jc ) can greatly improve the accuracy of the junction temperature estimation. the majority of the thermal energy of most ics is released into the pcb through the package leads, whereas only a small percentage of the total energy is released through the top of the case (where thermocouple measurements are usually conducted). the r jc resistance can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or when a heat sink is applied to an ic package. in all other cases, use of r jc will inaccurately estimate the true junction temperature. the jt parameter is experimentally derived by assuming that the dominant energy leaving through the top of the ic will be similar in both the testing environment and the application environment. as long as the recommended layout guidelines are observed, junction temperature estimations can be made accurately to within a few degrees celsius. 9.2.2.5 selecting v cc capacitor bypass capacitors for v cc is essential for achieving reliable performance. ti recommends choosing low-esr and low-esl, surface-mount, multi-layer ceramic capacitors (mlcc) with sufficient voltage ratings, temperature coefficients, and capacitance tolerances. a 50-v, 10- f mlcc and a 50-v, 0.22- f mlcc are selected for the c vcc capacitor. if the bias power supply output is located a relatively long distance from the v cc pin, a tantalum or electrolytic capacitor with a value greater than 10 f should be used in parallel with c vcc . note dc bias on some mlccs will impact the actual capacitance value. for example, a 25-v, 1- f x7r capacitor is measured to be only 500 nf when a dc bias of 15-v dc is applied. 10 power supply recommendations the recommended input supply voltage (v cc ) for the ucc23513 device is from 13.2 v to 33 v. the lower limit of the range of output bias-supply voltage (v cc ) is determined by the internal uvlo protection feature of the device. v cc voltage should not fall below the uvlo threshold for normal operation, or else the gate-driver outputs can become clamped low for more than 20 s by the uvlo protection feature. the higher limit of the v cc range depends on the maximum gate voltage of the power device that is driven by the ucc23513 device, and should not exceed the recommended maximum v cc of 33 v. a local bypass capacitor should be placed between the v cc and v ee pins, with a value of 220-nf to 10- f for device biasing. ti recommends placing an additional 100- nf capacitor in parallel with the device biasing capacitor for high frequency filtering. both capacitors should be positioned as close to the device as possible. low-esr, ceramic surface-mount capacitors are recommended. if only a single, primary-side power supply is available in an application, isolated power can be generated for the secondary side with the help of a transformer driver such as texas instruments' sn6501 or sn6505a . for such applications, detailed power supply design and transformer selection recommendations are available in sn6501 transformer driver for isolated power supplies data sheet and sn6505a low-noise 1-a transformer drivers for isolated power supplies data sheet . j c jt gd t t p < u advance information
23 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 layout 11.1 layout guidelines designers must pay close attention to pcb layout to achieve optimum performance for the ucc23513. some key guidelines are: ? component placement: ? low-esr and low-esl capacitors must be connected close to the device between the v cc and v ee pins to bypass noise and to support high peak currents when turning on the external power transistor. ? to avoid large negative transients on the v ee pins connected to the switch node, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized. ? grounding considerations: ? limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area is essential. this limitation decreases the loop inductance and minimizes noise on the gate terminals of the transistors. the gate driver must be placed as close as possible to the transistors. ? high-voltage considerations: ? to ensure isolation performance between the primary and secondary side, avoid placing any pcb traces or copper below the driver device. a pcb cutout or groove is recommended in order to prevent contamination that may compromise the isolation performance. ? thermal considerations: ? a large amount of power may be dissipated by the ucc23513 if the driving voltage is high, the load is heavy, or the switching frequency is high. proper pcb layout can help dissipate heat from the device to the pcb and minimize junction-to-board thermal impedance ( jb ). ? increasing the pcb copper connecting to the v cc and v ee pins is recommended, with priority on maximizing the connection to v ee . however, the previously mentioned high-voltage pcb considerations must be maintained. ? if the system has multiple layers, ti also recommends connecting the v cc and v ee pins to internal ground or power planes through multiple vias of adequate size. these vias should be located close to the ic pins to maximize thermal conductivity. however, keep in mind that no traces or coppers from different high voltage planes are overlapping. advance information
24 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated 11.2 layout example figure 20 shows a pcb layout example with the signals and key components labeled. (1) no pcb traces or copper are located between the primary and secondary side, which ensures isolation performance. figure 20. layout example advance information
25 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated layout example (continued) figure 21 and figure 22 show the top and bottom layer traces and copper. figure 21. top-layer traces and copper advance information
26 ucc23513 slusd31 ? october 2018 www.ti.com product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated layout example (continued) figure 22. bottom-layer traces and copper (flipped) advance information
27 ucc23513 www.ti.com slusd31 ? october 2018 product folder links: ucc23513 submit documentation feedback copyright ? 2018, texas instruments incorporated layout example (continued) figure 23 shows the 3d layout of the top view of the pcb. (1) the location of the pcb cutout between primary side and secondary sides ensures isolation performance. figure 23. 3-d pcb view 11.3 pcb material use standard fr-4 ul94v-0 printed circuit board. this pcb is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self- extinguishing flammability-characteristics. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 23-oct-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples PUCC23513DWY active soic dwy 6 64 tbd call ti call ti -40 to 130 ucc23513dwy preview 6 64 tbd call ti call ti -40 to 130 ucc23513dwyr preview 6 2500 tbd call ti call ti -40 to 130 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

▲Up To Search▲

Price & Availability of PUCC23513DWY

	To Download PUCC23513DWY Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .